Wafer-level batch packaging is under investigation by researchers to address the high power, input/output (I/O) density, and I/O bandwidth requirements of future technology generations (Naeemi, et al., Proc. IEEE International Solid State Circuits Conference, San Francisco, Calif., 280-281 (February 2001); International Technology Roadmap for Semiconductors (ITRS) (2001 update)). An optical interconnect technology conducive to wafer-level packaging is guided-wave optical interconnection. Optical waveguide interconnection allows for planar packaging of a hybrid electrical/optical system in a manner conducive to the delivery of future heat removal and power supply requirements. In addition, polymer waveguide technologies offer immediate, low-cost compatibility with wafer-level fabrication processes (Mule', et al., Procs. IEEE International Interconnect Technology Conference, San Francisco, Calif., 122-124 (June 2002)).
Integration of optical interconnection into microelectronic systems usually requires high-volume testability of optical interconnect components. Introductory technologies will likely involve the use of off-chip optical sources for intra-chip and inter-chip optical clock distribution and inter-chip and fiber-to-the-chip data communication. In each of these cases, chip-level detectors, waveguides, and diffractive optic devices will be integrated with CMOS microelectronics that require optical excitation in a manner representative of that found within a finished product. To provide for timely, low-cost, and high-volume testability, simultaneous electrical contact is made with chip-level I/O to provide for standard electrical testing. Finally, the density of electrical test I/O should match that of the chip under test, resulting in the need for an optoelectronic probe card capable of ultra-high-density electrical I/O. Thus, a heretofore unaddressed need exists in the microelectronics industry for a probe card that addresses the aforementioned deficiencies and/or inadequacies.